This invention relates to a semiconductor module, electronic equipment using the module and a method of manufacturing the same.
Heretofore, so-called multi-chip modules have been used for miniaturizing the size and improving the performance of electronic devices in which bare chips (various kinds of semiconductor devices and IC having desired functions in the shape of chips are collectively referred to as bare chips in this specification) and various kind of passive elements such as resistors, capacitors and coils are connected in plurality to each other to constitute a module.
However, in the existent multi-chip modules (MCM), since heat expansion coefficient is different for semiconductor chips, a substrate for mounting the semiconductor chips and substrate for mounting the substrate on which the semiconductor chips are mounted, thermal stress is generated during operation of the multi-chip module (MCM) to bring about a problem that a connection reliability can not be ensured.
Further, the manufacturing step for the multi-chip module (MCM) also involves the following problems. A ceramic wiring substrate for use in the multi-chip module is passed through the steps of baking and cooling during manufacture. In this process, the substrate is press bonded under lamination with a binder detaching from a green sheet and a conductor paste. Since deformation rate is different in each of them, wirings tend to be deformed in a case of a fine wiring pattern. Further, while they are cooled from the sintering temperature after the completion of the press bonding, since the ceramic substrate and the wiring material cause thermal deformation respectively also in this process, it was difficult to calculate the thermal deformation for the entire substrate and manufacture the multi-chip module. Accordingly, since the wiring width of the wiring substrate on which semiconductor chips are mounted increases, the number of layers of the wiring substrate increases making it difficult to attain thin and small mounting structure.
Japanese Patent Application Hei 8-527489 (International Laid-Open No. WO/97/03460) discloses a glass substrate for mounting semiconductor chips. However, the glass substrate is adapted to mount semiconductor chips on one surface but is not formed with wiring layers comprising insulation layers and conductor layers on both surfaces of the glass substrate.
Japanese Patent Laid-Open Hei 10-242206 discloses a substrate in which through holes are formed in light sensitive glass by using an exposure/developing process. The substrate has an aim of providing both a function as an inspection substrate during burn-in upon mounting bare chips and a function as an interposer (material interconnecting bare chip and an external terminal) for connection with a substrate such as a printed circuit board but it is not adapted to be formed with multiple wiring layers comprising insulation layers and conductor layers on a core substrate. Further, it does not disclose to form through holes by sand blasting.
Japanese Patent Laid-Open Hei 11-243267 discloses a wiring substrate in which wirings are formed on an insulation substrate having through holes. It is disclosed that the insulation substrate is formed of sintered ceramics such as sintered glass ceramics and manufactured, for example, by forming a ceramic green sheet, applying an appropriate punching to the ceramic green sheet into a predetermined shape and then sintering the same at a high temperature. Further, to form wirings which are less disconnected on the surface of the insulation substrate and the inner wall surface of the through holes, the diameter of the through hole is gradually enlarged from the center to both open ends of the substrate. As the method of forming the through hole, a method of using a trigonal drilling blade or a laser fabrication method is disclosed. However, the insulation substrate is made of glass ceramics and it is not a glass substrate, and multiple wiring layers comprising insulation layers and conductor layers are not formed on the insulation substrate.
This invention intends to provide a multi-chip module having improved connection reliability between semiconductor chips and a wiring substrate on which semiconductor chips are mounted, as well as improved connection reliability between the multi-chip module and a mounting substrate on which the multi-chip module is mounted.
As a result of research and development so far we have found that it is important to improve the constitution of a wiring substrate using a glass substrate having a surface smoothness and small heat expansion coefficient, as well as a manufacturing process therefor in order to provide a wiring substrate capable of high density wiring at a reduced cost.
We have also found that it is important to provide a multi-layered wiring substrate with a stress relieving mechanism in order to improve the connection reliability of an electronic device using the wiring substrate, for example, a multi-chip module.
Among the inventions disclosed in this application for attaining the foregoing object, outline of typical inventions is to be explained as below.
A multi-chip module includes semiconductor devices and a wiring substrate for mounting the semiconductor devices, wherein the wiring substrate comprises a glass substrate having holes for establishing electrical connection between both surfaces and plural wiring layers each formed on the surface of the glass substrate and having wirings (conductor layer) and an insulation layer, the diameter of the hole being enlarged from one open end to the other open end.
A multi-chip module includes semiconductor devices and a wiring substrate for mounting the semiconductor devices, wherein the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wirings and an insulation layer.
A multi-chip module as defined above, wherein the semiconductor devices and the wiring substrate are connected by means of a lead free solder.
A multi-chip module includes semiconductor devices and a wiring substrate for mounting the semiconductor devices, wherein the wiring substrate comprises a first substrate having through holes, a first wiring layer formed on one surface of the first substrate and having first wirings and a first insulation layer, a second wiring layer formed on the other surface of the first substrate and having second wirings and a second insulation layer, in which the heat expansion coefficient is different between the first wiring layer and the second wiring layer.
A multi-chip module as defined above, wherein the heat expansion coefficient of the first wiring layer is close to the heat expansion coefficient of the semiconductor device, and the heat expansion coefficient of the second wiring layer is close to the heat expansion coefficient of a mounting substrate for mounting the wiring substrate.
A multi-chip module has semiconductor devices and a wiring substrate for mounting the semiconductor devices, wherein the wiring substrate comprises a first substrate having through holes; a first wiring layer having first wirings and a first insulation layer formed to the surface of the first substrate on the side where the semiconductor devices are mounted; and a second wiring layer having second wirings and a second insulation layer formed to the surface of the first substrate on the side where the wiring substrate is mounted; wherein the heat expansion coefficient of the first wiring layer is close to the heat expansion coefficient of the semiconductor device, and the heat expansion coefficient of the second wiring layer is close to the heat expansion coefficient of a mounting substrate for mounting the wiring substrate.
A multi-chip module has semiconductor devices and a wiring substrate for mounting the semiconductor devices, wherein the wiring substrate comprises a first substrate having through holes with a heat expansion coefficient being from 3 ppm/xc2x0 C. to 5 ppm/xc2x0 C.; a first wiring layer formed on one surface of the first substrate having first wirings and a first insulation layer; a second wiring layer formed on one surface of the first substrate having second wirings and a second insulation layer; and a third insulation layer formed to the surface of the second wiring layer on the side opposite to the first substrate; wherein the modulus of elasticity of the third insulation layer is from 0.1 GPa to 10 GPa.
A multi-chip module comprises semiconductor devices and a wiring substrate for mounting the semiconductor devices, wherein the wiring substrate has a first substrate having through holes with a heat expansion coefficient being from 3 pm/xc2x0 C. to 5 ppm/xc2x0 C.; a first wiring layer having first wirings and a first insulation layer formed on one surface of the first substrate; a second wiring layer having second wirings and a second insulation layer formed on one surface of the first substrate; and a third insulation layer formed to the surface of the second wiring layer on the side opposite to the first substrate; wherein the third insulation layer relieves the thermal stresses caused between the wiring substrate and a mounting substrate for mounting the wiring substrate.
A method of manufacturing a multi-chip module comprises a step of forming a wiring layer having wirings and an insulation layer to at least one surface of a glass substrate, a step of forming holes in the glass substrate by sand blasting, and a step of mounting semiconductor devices on the wiring layer.
A method of manufacturing multi-chip module comprises a step of forming a first wiring layer including wirings and an insulation layer on one surface of a glass substrate, a step of forming a second insulation layer for relieving stresses caused between the glass substrate and a mounting substrate for mounting the wiring substrate, a step of forming first holes in the second insulation layer, a step of applying sand blasting to the first holes thereby forming second holes in the glass substrate, and a step of mounting a semiconductor device on the first wiring layer.
A method of manufacturing a multi-chip module comprises a step of forming a first wiring layer having a first wiring and a first insulation layer on one surface of the glass substrate, a step of forming a second wiring layer having second wirings and a second insulation layer on the other surface of the glass substrate, a step of forming a third insulation layer for relieving stresses caused between the glass substrate and a mounting substrate for mounting wiring substrate, a step of forming first holes in the third insulation layer, a step of conducting sand blasting to the first holes thereby forming second holes in the glass substrate, and a step of mounting semiconductor devices on the first wiring layer.
A method of manufacturing a multi-chip module comprising a step of forming through holes in a glass substrate by sand blasting, a step of forming first wirings on the inner wall surface of the through holes and on the glass substrate, a step of filling the through holes with an electric conductive material or insulation material, a step of forming a first insulation layer on one surface of the glass substrate, a step of forming a second insulation layer on the other surface of the glass substrate, a step of forming holes in the second insulation layer, a step of forming second wirings on the inner wall surface of the hole in the second insulation layer, a step of forming third wirings to the surface of the first insulation layer on the side opposite to the glass substrate, and a step of mounting semiconductor devices on the first insulation layer so as to establish an electrical connection with respect to the third wiring.
A method of manufacturing a multi-chip module comprises a step of preparing a wiring substrate including a glass substrate having holes for establishing electrical connection on both surfaces and a plurality of wiring layers having a wiring and an insulation layer formed on the glass substrate, a step of mounting plural semiconductor devices on the wiring substrate, a step of conducting a test between semiconductor devices, and a step of replacing the semiconductor devices in accordance with the result of the operation test and a step of separating the wiring substrate into individual portions.